? semiconductor components industries, llc, 2013 july, 2013 ? rev. 0 1 publication order number: cav93c46/d cav93c46 1-kb microwire serial eeprom description the cav93c46 is a 1 ? kb serial eeprom memory device which is configured as either 64 registers of 16 bits (org pin at v cc ) or 128 registers of 8 bits (org pin at gnd). each register can be written (or read) serially by using the di (or do) pin. the cav93c46 features a self ? timed internal write with auto ? clear. on ? chip power ? on reset circuit protects the internal logic against powering up in the wrong state. features ? automotive temperature grade 1 ( ? 40 c to +125 c) ? high speed operation: 2 mhz ? 2.5 v to 5.5 v supply voltage range ? selectable x8 or x16 memory organization ? self ? timed write cycle with auto ? clear ? sequential read ? software write protection ? power ? up inadvertant write protection ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? 8 ? pin soic and tssop packages ? this device is pb ? free, halogen free/bfr free and rohs compliant ? figure 1. functional symbol do gnd cav93c46 v cc org cs sk di ?for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. pin configurations gnd nc v cc do di sk cs 1 org soic (v), tssop (y) (top view) http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information chip select cs clock input sk serial data input di serial data output do power supply v cc ground gnd function pin name pin function memory organization org no connection nc note: when the org pin is connected to v cc , the x16 organization is selected. when it is connected to ground, the x8 organization is selected. if the org pin is left unconnected, then an internal pullup device will select the x16 organization. soic ? 8 v suffix case 751bd tssop ? 8 y suffix case 948al
cav93c46 http://onsemi.com 2 table 1. absolute maximum ratings parameter value units storage temperature ? 65 to +150 c voltage on any pin with respect to ground (note 1) ? 0.5 to +6.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the dc input voltage on any pin should not be lower than ? 0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than ? 1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. table 2. reliability characteristics (note 2) symbol parameter min units n end (note 3) endurance 1,000,000 program / erase cycles t dr data retention 100 years 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 3. block mode, v cc = 5 v, 25 c table 3. d.c. operating characteristics (v cc = +2.5 v to +5.5 v, t a = ? 40 c to +125 c, unless otherwise specified.) symbol parameter test conditions min max units i cc1 supply current (write) write, v cc = 5.0 v 1 ma i cc2 supply current (read) read, do open, f sk = 2 mhz, v cc = 5.0 v 500 a i sb1 standby current (x8 mode) v in = gnd or v cc cs = gnd, org = gnd 5 a i sb2 standby current (x16 mode) v in = gnd or v cc cs = gnd, org = float or v cc 3 a i li input leakage current v in = gnd to v cc 2 a i lo output leakage current v out = gnd to v cc cs = gnd 2 a v il1 input low voltage 4.5 v v cc < 5.5 v ? 0.1 0.8 v v ih1 input high voltage 4.5 v v cc < 5.5 v 2 v cc + 1 v v il2 input low voltage 2.5 v v cc < 4.5 v 0 v cc x 0.2 v v ih2 input high voltage 2.5 v v cc < 4.5 v v cc x 0.7 v cc + 1 v v ol1 output low voltage 4.5 v v cc < 5.5 v, i ol = 3 ma 0.4 v v oh1 output high voltage 4.5 v v cc < 5.5 v, i oh = ? 400 a 2.4 v v ol2 output low voltage 2.5 v v cc < 4.5 v, i ol = 1 ma 0.2 v v oh2 output high voltage 2.5 v v cc < 4.5 v, i oh = ? 100 a v cc ? 0.2 v table 4. pin capacitance (t a = 25 c, f = 1 mhz, v cc = 5 v) symbol test conditions min typ max units c out (note 4) output capacitance (do) v out = 0 v 5 pf c in (note 4) input capacitance (cs, sk, di, org) v in = 0 v 5 pf 4. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods.
cav93c46 http://onsemi.com 3 table 5. a.c. characteristics (v cc = +2.5 v to +5.5 v, t a = ? 40 c to +125 c, unless otherwise specified.) symbol parameter min max units t css cs setup time 50 ns t csh cs hold time 0 ns t dis di setup time 100 ns t dih di hold time 100 ns t pd1 output delay to 1 0.25 s t pd0 output delay to 0 0.25 s t hz (note 5) output delay to high ? z 100 ns t ew program/erase pulse width 5 ms t csmin minimum cs low time 0.25 s t skhi minimum sk high time 0.25 s t sklow minimum sk low time 0.25 s t sv output delay to status valid 0.25 s sk max maximum clock frequency dc 2000 khz 5. this parameter is tested initially and after a design or process change that affects the parameter. table 6. power ? up timing (notes 6 and 7) symbol parameter max units t pur power ? up to read operation 1 ms t puw power ? up to write operation 1 ms 6. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 7. t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. table 7. a.c. test conditions input rise and fall times 50 ns input pulse voltages 0.4 v to 2.4 v 4.5 v v cc 5.5 v timing reference voltages 0.8 v, 2.0 v 4.5 v v cc 5.5 v input pulse voltages 0.2 v cc to 0.7 v cc 2.5 v v cc 4.5 v timing reference voltages 0.5 v cc 2.5 v v cc 4.5 v output load current source i olmax /i ohmax ; c l = 100 pf
cav93c46 http://onsemi.com 4 device operation the cav93c46 is a 1024 ? bit nonvolatile memory intended for use with industry standard microprocessors. the cav93c46 can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 9 ? bit instructions control the reading, writing and erase operations of the device. when organized as x8, seven 10 ? bit instructions control the reading, writing and erase operations of the device. the cav93c46 operates on a single power supply and will generate on chip the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status during a write operation. the serial communication protocol follows the timing shown in figure 2. the ready/busy status can be determined after the start of internal write cycle by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy ?1? into the di pin. the do pin will enter the high impedance state on the rising edge of the clock (sk). placing the do pin into the high impedance state is recommended in applications where the di pin and the do pin are to be tied together to form a common di/o pin. the ready/busy flag can be disabled only in ready state; no change is allowed in busy state. the format for all instructions sent to the device is a logical ?1? start bit, a 2 ? bit (or 4 ? bit) opcode, 6 ? bit address (an additional bit when organized x8) and for write operations a 16 ? bit data field (8 ? bit for x8 organization). read upon receiving a read command (figure 3) and an address (clocked into the di pin), the do pin of the cav93c46 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). after the initial data word has been shifted out and cs remains asserted with the sk clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential read mode. as long as cs is continuously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is proceeded by a dummy zero bit. all sunsequent data words will follow without a dummy zero bit. erase/write enable and disable the cav93c46 powers up in the write disable state. any writing after power ? up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cav93c46 write and erase instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. the ewen and ewds instructions timing is shown in figure 4. table 8. instruction set instruction start bit opcode address data comments x8 x16 x8 x16 read 1 10 a6 ? a0 a5 ? a0 read address an?a0 erase 1 11 a6 ? a0 a5 ? a0 clear address an?a0 write 1 01 a6 ? a0 a5 ? a0 d7 ? d0 d15 ? d0 write address an?a0 ewen 1 00 11xxxxx 11xxxx write enable ewds 1 00 00xxxxx 00xxxx write disable eral 1 00 10xxxxx 10xxxx clear all addresses wral 1 00 01xxxxx 01xxxx d7 ? d0 d15 ? d0 write all addresses
cav93c46 http://onsemi.com 5 figure 2. synchronous data timing sk di cs do valid data valid t csh t dih t csmin t dis t pd0 , t pd1 valid t dis t css t skhi t sklow figure 3. read instruction timing sk cs di do high ? z 11 0 dummy 0 don?t care a n a n ? 1 t pd0 a 0 address + n d 15 . . . or d 7 . . . address + 2 d 15 . . . d 0 or d 7 . . . d 0 address + 1 d 15 . . . d 0 or d 7 . . . d 0 d 15 . . . d 0 or d 7 . . . d 0 figure 4. ewen/ewds instruction timing cs di standby 0 * * enable = 11 disable = 00 sk 0 1
cav93c46 http://onsemi.com 6 write after receiving a write command (figure 5), address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking for auto ? clear and data store cycles on the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the ca v93c46 can be determined by selecting the device and polling the do pin. since this device features auto ? clear before write, it is not necessary to erase a memory location before it is written into. erase upon receiving an erase command and address, the cs (chip select) pin must be de ? asserted for a minimum of t csmin (figure 6). the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cav93c46 can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical ?1? state. erase all upon receiving an eral command (figure 7), the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cav93c46 can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical ?1? state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin (figure 8). the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cav93c46 can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. figure 5. write instruction timing sk cs di do standby high ? z high ? z 101 busy ready status verify a n a n ? 1 a 0 d n d 0 t csmin t ew t sv t hz
cav93c46 http://onsemi.com 7 figure 6. erase instruction timing sk cs di do standby high ? z high ? z 1 busy ready status verify 11 a n a n ? 1 a 0 t cs min t sv t hz t ew figure 7. eral instruction timing sk cs di do standby high ? z high ? z 10 1 busy ready status verify 00 t cs min t hz t sv t ew figure 8. wral instruction timing status verify sk cs di do standb y high ? z 10 1 busy ready 0 0 d n d 0 t csmin t ew t sv t hz
cav93c46 http://onsemi.com 8 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35
cav93c46 http://onsemi.com 9 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
cav93c46 http://onsemi.com 10 example of ordering information device order number specific device marking package type temperature range lead finish shipping cav93c46ve ? gt3 93c46p soic ? 8, jedec ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel cav93c46ye ? gt3 m46p tssop ? 8 ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel 8. all packages are rohs ? compliant (lead ? free, halogen ? free). 9. the standard lead finish is nipdau. 10. for additional package and temperature options, please contact your nearest on semiconductor sales office. 11. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. 12. for detailed information and a breakdown of device nomenclature and numbering systems, please see the on semiconductor devic e nomenclature document, tnd310/d, available at www.onsemi.com on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 cav93c46/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
